The present invention relates to a semiconductor device and a method for producing a semiconductor device by means of the passive isolation method, hereinafter referred to as the PI method. More particularly, the present invention relates to an improved means of forming an electrode which is electrically connected to the substrate of the semiconductor device. This electrode is hereinafter referred to as the substrate electrode.
Art prior to the present invention is explained with reference to FIGS. 1A, 1B, 2A, 2B, and 2C.
The isolation method used in the case of bipolar ICs is either a PN junction isolation method illustrated in FIG. 1A or a PI method illustrated in FIG. 1B. The latter method of isolation is superior to the former method of isolation because the elements of the bipolar ICs can be formed having a high integration density. More specifically, in the PN junction isolation method FIG. 1A, an N-type epitaxial layer 2 having a thickness of approximately 3 microns is formed on the P type silicon semiconductor substrate 1. The elements of the bipolar ICs, the transistor elements for example, are then formed on the N type epitaxial layer 2. Only one region in which one of the transistors is formed is shown in FIG. 1A and is denoted by the numeral 3. This region is hereinafter simply referred to as the element-forming region 3. In order to isolate each element-forming region 3 from the other element-forming regions (not shown), a P.sup.+ -type isolation region 4 is formed in the N-type epitaxial layer 2 by means of thermal diffusion of the P-type impurities. Since the P-type impurities diffuse laterally into the N-type epitaxial layer in a larger area than the area required in the PI method, dimension tolerance L.sub.1 and L.sub.2, such that the P.sup.+ -type isolation region 4 is in contact with neither the P-type base region 5 nor the N.sup.+ -type collector contact region 6, must be provided before thermal diffusion is performed, and therefore the integration density is disadvantageously low. However, a high integration density can be achieved in the bipolar IC illustrated in FIG. IB by means of the PI method because contact between the P-type base region 5 or the N.sup.+ -type collector contact region 6 and the isolation region 7 does not result in disadvantages at all due to the fact that the isolation region 7 is an insulator. The isolation region 7 consists of a silicon dioxide film or an insulating material. As is apparent from a comparison of FIG. 1B and FIG. 1A, the element-forming region 3 in FIG. 1B is smaller than that in FIG. 1A, and the N-type epitaxial layer 2 can be used effectively for forming the elements of the bipolar ICs. Nevertheless, the formation of the substrate electrode by means of the PI method involves a problem. Referring again to FIG. 1A, since the P.sup.+ -type isolation region 4 is electrically connected to the P-type silicon semiconductor substrate 1, the formation of the substrate electrode can be simply achieved by depositing the electrode material on the surface of the P.sup.+ -type isolation region 4. In other words, the region 4 can be used not only as a PN junction isolation region but also as a means of electrically connecting the P-type electrode material and the silicon semiconductor substrate 1. However, in the case of the PI method the isolation region 7 cannot be used as a means of electrically connecting the electrode material and the silicon semiconductor substrate because the isolation region 7 is insulative.
The reference numerals 8 and 9 in FIGS. 1A and 1B indicate the emitter region and the N.sup.+ -type buried layer, respectively.
In an attempt to solve the problem involved in the PI method, the semiconductor devices shown in FIGS. 2A, 2B, and 2C have been produced. However, the problem has not been completely solved.
Referring to FIG. 2A, an IC chip 11, in which the bipolar ICs are fabricated, is mounted on a package 10 made of ceramics or the like. The IC chip 11 is thermally bonded to a thin gold layer 12 which is formed by placing a gold pellet (not shown) on the bottom of the recess of the package 10 and then frictionally rubbing the chip over the gold pellet, which is, in turn, flattened and applied to the bottom. The thin gold layer 12 makes possible the easy formation of the substrate electrode. A terminal chip 13 made of metal or silicon is thermally bonded to the thin gold layer 12 and then a wire 15 is strung between the terminal chip 13 and the lead terminal 14, with the result that a path of current or an electric lead is formed between the lead terminal 14 and the silicon semiconductor substrate (not shown) via the bottom surface of the IC chip 11. This process does not involve a complicated bonding operation. However, the construction of and production process of an electronic device are complicated since the terminal chip 13 is indispensible, that is, a path of current cannot be formed by means of the IC chip 11 itself. In addition, in a case where the integration of the bipolar ICs of the IC chip becomes large, the dimension of the IC chip 11 is accordingly so large that no space is left for positioning the terminal chip 13. Instead of forming a thin gold layer 12 by means of a gold pellet, the layer 12 is deposited on the package 10 beforehand, which however, is expensive. Furthermore, the thin gold layer 12 may extend from the bottom of the recess of the package 10 to the top, but this is also expensive.
Referring to FIG. 2B, the substrate electrode is formed on the top surface of the IC chip. The isolation method carried out in the device shown in FIG. 2B is a method of isolation using oxide and poly-silicon and is referred to as the IOP (Isolation by Oxide and Poly-Silicon) method. In the IOP method, a V groove (V-ATE) 20 is formed by subjecting the (100) surface of the silicon semiconductor substrate 1 to anisotropic etching. The impurities having the same conductivity type as that of the silicon semiconductor substrate, i.e. P-type in FIG. 2B, are shallowly introduced into the V-ATE 20 from the surface of the V-ATE 20, thereby forming a P-type diffusion layer 21. Insulating material, such as polycrystalline silicon, is embedded in the V-ATE 20 (the embedded insulating material is not shown in FIG. 2B). The formation of the substrate electrode can be achieved by depositing aluminum 22 on the surface of the N-type epitaxial layer 2 in such a manner that the aluminum 22 is in ohmic contact with the P-type diffusion layer 21. In the IOP method, the V-ATE 20, in which the insulating material is embedded, protrudes into and through the N type epitaxial layer 2 and forms an isolation region. In other words, isolation of the element-forming region 3 from the other element-forming regions is complete even if the P-type diffusion layer 21 is not formed around the V-ATE 20. However, if the P-type diffusion layer 21 is formed around the V-ATE 20, a PN junction isolation region is formed between the N-type epitaxial layer 2 and the P-type diffusion layer 21, and the advantages of the PI method are lost. Therefore, a dimension tolerance, as is necessary in the case of the PN junction isolation method, is also necessary in the case of the IOP method. An advantage of the PI method basically resides in the self-alignment of the base and/or emitter regions, the advantage is lost, however, in the case of the formation of the P-type diffusion layer 21.
Referring to FIG. 2C, the structure of the device formed according to the PI method as shown in FIG. 1B is unchanged, and, in addition to this structure, a P.sup.+ -type diffusion layer 23, which is so deep that it penetrates through the N-type epitaxial layer 2 into the P-type silicon semiconductor substrate 1, is formed in such a manner that it surrounds the element-forming region 3 and the isolation region 7. The P.sup.+ -type diffusion layer 23 is used to form the substrate electrode because when a diffusion layer is used there is no decrease in the integration density since the P.sup.+ -type diffusion layer 23 is formed in a vacant space, i.e. in the part of the N-type epitaxial layer 2 which is located between the neighbouring isolation regions (one of which is shown as "7"). Part of the vacant space in which the P.sup.+ -type diffusion layer 23 is formed is not part of the element-forming region 3. In order to form the P.sup.+ -type diffusion layer 23, a heat treatment of approximately 1000.degree. C. is carried out. The heat treatment results in upward diffusion of the N-type impurities of the N.sup.+ -type buried layer 9. The effective thickness of the N-type epitaxial layer 2 is decreased during the heat treatment to such an extent that the diffusion of P-type impurities in the formation of the P-type base region 5 at a later stage is likely to result in contact or near contact between the N.sup.+ -type buried layer 9 and the P-type base region 5. Thus, the breakdown voltage of the device is decreased.